The present invention relates to semiconductor technology, and more particularly to use of auxiliary substrates for interconnection of semiconductor integrated circuits and other components.
Semiconductor integrated circuits (ICs) are miniature devices with tiny contact pads that must be connected to other IC or non-IC components. The connection to other components is facilitated by auxiliary substrates such as printed circuit boards (PCBs) or interposers. FIG. 1 illustrates ICs 110 connected to a PCB 114 through an interposer 120. ICs 110 have contact pads 112 attached to contact pads 120C.T on top of interposer 120. The attachment is via connections 140 that can be solder, adhesive, or thermocompression for example. The interposer's bottom contact pads 120C.B are attached to the PCB's contact pads 114C (by suitable connections 140). Interconnect lines 120L in interposer 120 provide desired connection between the interposer's contact pads 120C (i.e. 120C.T and 120C.B). The PCB's interconnect lines 114L provide desired connection between the PCB's contact pads 114C. Other interposers, ICs, or other circuits can be connected to the PCB.
To provide small size, high operating speed, low power consumption, and low manufacturing cost, each component 110, 114, 120 may have densely packed circuitry with correspondingly densely packed contact pads 112, 114C, 120C and preferably short interconnect lines (“wires”) 114L, 120L. In particular, the interposer 120 should be thin to shorten the vertical segments of lines 120L. Thin interposers can be inexpensively fabricated from organic or ceramic materials. However, a thin interposer can be fragile and flexible and can be easily warped or broken by mechanical stresses, such as thermal stresses arising from thermal expansion. Thermal stresses are particularly damaging in the presence of materials with different coefficients of thermal expansion (CTEs). For example, silicon has a lower CTE than organic or ceramic materials commonly used in PCBs and interposers, and this is a serious problem for using organic or ceramic PCBs and interposers with silicon-based ICs. Thermal stresses can damage the connections 140 and make the assembly inoperable. Also, thermal stresses contribute to warpage which complicates the assembly process.
Therefore, it is desired to stiffen the interposer against warpage and also to use thermally conductive materials that spread locally generated heat and conduct such heat into the ambient.
FIG. 2 illustrates a known ceramic or organic interposer 120 with a cover 210 over a die 110 (a die is an IC that was manufactured as part of a semiconductor wafer and then separated from the wafer; the wafer may contain multiple dies fabricated at the same time). The interposer connects the die 110 to bottom contact pads 120C.B; lines 120L are not shown. Cover 210 is attached to interposer 120 by epoxy 220. Cover 210 stiffens and flattens the interposer, and acts like a heat spreader: the heat generated by die 110 is conducted through thermal grease 230 to cover 210 and then to the ambient. See U.S. Pat. No. 7,061,102 issued Jun. 13, 2006 to Eghan et al.
In order to reduce thermal stresses at the interface between stiffener 210 and interposer 120, the stiffener and the interposer can be made in a single substrate 120S as shown in FIG. 3 and described in the Eghan patent. Substrate 120S has a cavity 304 containing the die 110; the die is surrounded by the substrate's “perimeter wall” 304P. The assembly can be further strengthened by underfill 310 between the die and the interposer: the underfill is made of epoxy that glues the die to the interposer and thus relieves the stress on connections 140. Also, the underfill can be thermally conductive to spread the heat. In addition, thermally conductive encapsulant 320 fills the spaces between the die and the walls 304P to protect the die and help in heat spreading. The encapsulant may or may not cover the die, and an additional heat spreader (not shown) may be provided on top.
FIG. 4 illustrates an organic (molded epoxy or plastic) interposer 120 supporting a stack of three dies 110.1, 110.2, 110.3, as described in U.S. Pat. No. 6,492,726 (Quek et al., Dec. 10, 2002). Here the interposer cavity 304 has stepped sidewalls, with different dies 110.1, 110.2, 110.3 mounted on respective different steps 410.1, 410.2, 410.3 (410.1 is the cavity bottom). For each step, contact structures 420 extend from the respective “contact balls” 140 down through the interposer where they can be accessed from below the interposer. See also U.S. Pat. No. 7,977,579 (Bathan et al., Jul. 12, 2011).
The dies 110 (i.e. 110.1, 110.2, 110.3) of FIG. 4 can be underfilled and encapsulated with suitable dielectric materials (not shown). A heat spreader (not shown) can be provided on top.